1. Technical Field
This invention relates to digital computer systems and more particularly to digital computer systems utilizing cache memory arrangements.
2. Description of the Prior Art
Cache memory is useful to increase the throughput of a digital computer system. A cache memory system includes a small but relatively fast memory that temporarily contains information recently used by the central processor. During a read by the processor of main memory, the cache memory performs a memory cycle to determine whether the information being sought is contained in cache. If the information is present in cache--termed a "hit"--the information is returned to the processor and main memory is not accessed. If the information is not present--a "miss"--the information is read from main memory, returned to the central processor and written into cache for subsequent access as needed. During a write of information by the central processor to main memory the cache performs a memory cycle to determine if the information is present. If so, a control bit is reset in cache--a validity bit or V-bit--to indicate that the information word in cache has been superceded and is invalid. Alternatively, during a write of main memory the new information word may be written also into cache.
Direct memory access ("DMA") is also useful in digital computer systems. Direct memory access is typically used in conjunction with relatively slow bulk storage input-output devices such as disc storage. In response to a central processor request for input-output transfer--e.g. a read or write--to main memory, the DMA autonomously performs data transfer directly between the input-output device and main memory. The DMA steals main memory cycles as necessary to complete the requested transfer and typically interrupts the central processor when complete. DMA transfer may comprise the transfer of a single word of information, useful for moving data words for processing, or may comprise the transfer of a plurality of information words in a contiguous block. Block transfer is particularly useful for loading computer programs into main memory from input-output devices, such as occurs during swapping or paging.
A problem arises when a cache memory system of the type described above is utilized in conjunction with direct memory access. During a block DMA write it is preferred that the central processor remain free to execute instructions from cache. In practice, however, DMA operation requires a certain number of the available cache memory cycles. As each word of the block is transferred by DMA to main memory, the cache memory performs a necessary invalidation memory cycle in order to determine if each newly written word is present in cache and, if so, to reset its validity bit. The central processor is not able to access cache during the invalidation cycle so that program execution is momentarily suspended. If the number of words in a block is great, the number of required cache cycles is correspondingly great. It is desirable to reduce the number of cache invalidation memory cycles required for a block DMA transfer in order to increase the number of cache memory cycles available to the central processor.
Block DMA operation has correspondingly greater impact on multi-processor systems where each processor is associated with its own cache memory system. Each cache may be required to perform all invalidation memory cycles during a block DMA write, interfering with the operation of each processor and reducing overall throughput of the multi-processor system.